Symbolics I - machine architecture - a symbolic processor architecture for VLSI implementation

Bruce Edwards; Greg Efland; Neil Weste

Symbolics I - machine architecture - a symbolic processor architecture for VLSI implementation

Bruce Edwards^*, Greg Efland, Neil Weste

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

Abstract

The authors describe features of the I-machine family, a third-generation symbolic processor architecture. The architecture is based on experience gained with the Symbolics 3600 and is targeted for a single-chip CMOS VLSI implementation.

Original language	English
Title of host publication	IEEE International Conference on Computer Design, VLSI in computers & processors : ICCD '87, Rye Town Hilton, Rye Brook, N.Y.
Place of Publication	Washington, DC
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	502-505
Number of pages	4
ISBN (Print)	0818608021
Publication status	Published - 1987
Externally published	Yes

Cite this

@inproceedings{f844c8ce940346a18041fb105afd4890,

title = "Symbolics I - machine architecture - a symbolic processor architecture for VLSI implementation",

abstract = "The authors describe features of the I-machine family, a third-generation symbolic processor architecture. The architecture is based on experience gained with the Symbolics 3600 and is targeted for a single-chip CMOS VLSI implementation.",

author = "Bruce Edwards and Greg Efland and Neil Weste",

year = "1987",

language = "English",

isbn = "0818608021",

pages = "502--505",

booktitle = "IEEE International Conference on Computer Design, VLSI in computers & processors : ICCD '87, Rye Town Hilton, Rye Brook, N.Y.",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

}

Symbolics I - machine architecture - a symbolic processor architecture for VLSI implementation. / Edwards, Bruce; Efland, Greg; Weste, Neil.
IEEE International Conference on Computer Design, VLSI in computers & processors : ICCD '87, Rye Town Hilton, Rye Brook, N.Y.. Washington, DC: Institute of Electrical and Electronics Engineers (IEEE), 1987. p. 502-505.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

TY - GEN

T1 - Symbolics I - machine architecture - a symbolic processor architecture for VLSI implementation

AU - Edwards, Bruce

AU - Efland, Greg

AU - Weste, Neil

PY - 1987

Y1 - 1987

N2 - The authors describe features of the I-machine family, a third-generation symbolic processor architecture. The architecture is based on experience gained with the Symbolics 3600 and is targeted for a single-chip CMOS VLSI implementation.

AB - The authors describe features of the I-machine family, a third-generation symbolic processor architecture. The architecture is based on experience gained with the Symbolics 3600 and is targeted for a single-chip CMOS VLSI implementation.

UR - http://www.scopus.com/inward/record.url?scp=0023567818&partnerID=8YFLogxK

M3 - Conference proceeding contribution

AN - SCOPUS:0023567818

SN - 0818608021

SP - 502

EP - 505

BT - IEEE International Conference on Computer Design, VLSI in computers & processors : ICCD '87, Rye Town Hilton, Rye Brook, N.Y.

PB - Institute of Electrical and Electronics Engineers (IEEE)

CY - Washington, DC

ER -

Symbolics I - machine architecture - a symbolic processor architecture for VLSI implementation

Abstract

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