Symbolics ivory processor

a 40 bit tagged architecture lisp microprocessor.

Clark Baker*, David Chan, Jim Cherry, Alan Corry, Greg Efland, Bruce Edwards, Mark Matson, Henry Minsky, Eric Nestler, Kalman Reti, David Sarrazin, Charles Sommer, David Tan, Neil Weste

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contribution

2 Citations (Scopus)

Abstract

A description is given of the VLSI implementation of a third-generation symbolic processor optimized for the Lisp language. The design effort has resulted in a single-chip implementation of a complete CPU which efficiently executes Lisp primitives and offers performances, system integration, and manufacturability advantages over current approaches to Lisp processors. These advantages are outlined.

Original languageEnglish
Title of host publication 1987 IEEE International Conference on Computer Design, VLSI in computers & processors : ICCD '87, Rye Town Hilton, Rye Brook, N.Y.
Place of PublicationWashington, DC
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages512-515
Number of pages4
ISBN (Print)0818608021
Publication statusPublished - 1987
Externally publishedYes

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  • Cite this

    Baker, C., Chan, D., Cherry, J., Corry, A., Efland, G., Edwards, B., ... Weste, N. (1987). Symbolics ivory processor: a 40 bit tagged architecture lisp microprocessor. In 1987 IEEE International Conference on Computer Design, VLSI in computers & processors : ICCD '87, Rye Town Hilton, Rye Brook, N.Y. (pp. 512-515). Washington, DC: Institute of Electrical and Electronics Engineers (IEEE).