Symbolics ivory processor: a 40 bit tagged architecture lisp microprocessor.

Clark Baker; David Chan; Jim Cherry; Alan Corry; Greg Efland; Bruce Edwards; Mark Matson; Henry Minsky; Eric Nestler; Kalman Reti; David Sarrazin; Charles Sommer; David Tan; Neil Weste

Symbolics ivory processor

a 40 bit tagged architecture lisp microprocessor.

Clark Baker^*, David Chan, Jim Cherry, Alan Corry, Greg Efland, Bruce Edwards, Mark Matson, Henry Minsky, Eric Nestler, Kalman Reti, David Sarrazin, Charles Sommer, David Tan, Neil Weste

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution

2 Citations (Scopus)

Abstract

A description is given of the VLSI implementation of a third-generation symbolic processor optimized for the Lisp language. The design effort has resulted in a single-chip implementation of a complete CPU which efficiently executes Lisp primitives and offers performances, system integration, and manufacturability advantages over current approaches to Lisp processors. These advantages are outlined.

Original language	English
Title of host publication	1987 IEEE International Conference on Computer Design, VLSI in computers & processors : ICCD '87, Rye Town Hilton, Rye Brook, N.Y.
Place of Publication	Washington, DC
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	512-515
Number of pages	4
ISBN (Print)	0818608021
Publication status	Published - 1987
Externally published	Yes

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Baker, C., Chan, D., Cherry, J., Corry, A., Efland, G., Edwards, B., ... Weste, N. (1987). Symbolics ivory processor: a 40 bit tagged architecture lisp microprocessor. In 1987 IEEE International Conference on Computer Design, VLSI in computers & processors : ICCD '87, Rye Town Hilton, Rye Brook, N.Y. (pp. 512-515). Washington, DC: Institute of Electrical and Electronics Engineers (IEEE).

Baker, Clark ; Chan, David ; Cherry, Jim ; Corry, Alan ; Efland, Greg ; Edwards, Bruce ; Matson, Mark ; Minsky, Henry ; Nestler, Eric ; Reti, Kalman ; Sarrazin, David ; Sommer, Charles ; Tan, David ; Weste, Neil. / Symbolics ivory processor : a 40 bit tagged architecture lisp microprocessor. 1987 IEEE International Conference on Computer Design, VLSI in computers & processors : ICCD '87, Rye Town Hilton, Rye Brook, N.Y.. Washington, DC : Institute of Electrical and Electronics Engineers (IEEE), 1987. pp. 512-515

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title = "Symbolics ivory processor: a 40 bit tagged architecture lisp microprocessor.",

abstract = "A description is given of the VLSI implementation of a third-generation symbolic processor optimized for the Lisp language. The design effort has resulted in a single-chip implementation of a complete CPU which efficiently executes Lisp primitives and offers performances, system integration, and manufacturability advantages over current approaches to Lisp processors. These advantages are outlined.",

author = "Clark Baker and David Chan and Jim Cherry and Alan Corry and Greg Efland and Bruce Edwards and Mark Matson and Henry Minsky and Eric Nestler and Kalman Reti and David Sarrazin and Charles Sommer and David Tan and Neil Weste",

year = "1987",

language = "English",

isbn = "0818608021",

pages = "512--515",

booktitle = "1987 IEEE International Conference on Computer Design, VLSI in computers & processors : ICCD '87, Rye Town Hilton, Rye Brook, N.Y.",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

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Baker, C, Chan, D, Cherry, J, Corry, A, Efland, G, Edwards, B, Matson, M, Minsky, H, Nestler, E, Reti, K, Sarrazin, D, Sommer, C, Tan, D & Weste, N 1987, Symbolics ivory processor: a 40 bit tagged architecture lisp microprocessor. in 1987 IEEE International Conference on Computer Design, VLSI in computers & processors : ICCD '87, Rye Town Hilton, Rye Brook, N.Y.. Institute of Electrical and Electronics Engineers (IEEE), Washington, DC, pp. 512-515.

Symbolics ivory processor : a 40 bit tagged architecture lisp microprocessor. / Baker, Clark; Chan, David; Cherry, Jim; Corry, Alan; Efland, Greg; Edwards, Bruce; Matson, Mark; Minsky, Henry; Nestler, Eric; Reti, Kalman; Sarrazin, David; Sommer, Charles; Tan, David; Weste, Neil.

1987 IEEE International Conference on Computer Design, VLSI in computers & processors : ICCD '87, Rye Town Hilton, Rye Brook, N.Y.. Washington, DC : Institute of Electrical and Electronics Engineers (IEEE), 1987. p. 512-515.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution

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AU - Baker, Clark

AU - Chan, David

AU - Cherry, Jim

AU - Corry, Alan

AU - Efland, Greg

AU - Edwards, Bruce

AU - Matson, Mark

AU - Minsky, Henry

AU - Nestler, Eric

AU - Reti, Kalman

AU - Sarrazin, David

AU - Sommer, Charles

AU - Tan, David

AU - Weste, Neil

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AB - A description is given of the VLSI implementation of a third-generation symbolic processor optimized for the Lisp language. The design effort has resulted in a single-chip implementation of a complete CPU which efficiently executes Lisp primitives and offers performances, system integration, and manufacturability advantages over current approaches to Lisp processors. These advantages are outlined.

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SN - 0818608021

SP - 512

EP - 515

BT - 1987 IEEE International Conference on Computer Design, VLSI in computers & processors : ICCD '87, Rye Town Hilton, Rye Brook, N.Y.

PB - Institute of Electrical and Electronics Engineers (IEEE)

CY - Washington, DC

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