Systolic variable length architecture for discrete fourier transform in long term evolution

C. V. Niras, Vinu Thomas

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contribution

3 Citations (Scopus)

Abstract

A novel design for the implementation of the 2-M x 3-P x 5Q point Discrete Fourier Transform (DFT) computation for Single Carrier-Frequency Division Multiple Access (SC-FDMA) systems as defined by the Long Term Evolution standard is proposed. The design is based on the Systolic Architecture. The decomposition of the DFT computation into factors of two, three, four and five is implemented by a recursive invocation of the Cooley-Tukey Algorithm, with the individual DFTs within each Cooley Tukey iteration implemented using the Winograd Fourier Transform Algorithm (WFTA). The proposed architecture is superior to the Intellectual Property (IP) cores proposed by Xilinx R in that the clock frequency requirements are reduced by a factor of up to 5.2 (approx), resulting in significant savings in the total power dissipation.

Original languageEnglish
Title of host publicationISED 2012
Subtitle of host publicationProceedings of the 2012 International Symposium on Electronic System Design
Place of PublicationPiscataway, NJ
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages52-55
Number of pages4
ISBN (Print)9780769549026
DOIs
Publication statusPublished - 2012
Externally publishedYes
Event2012 International Symposium on Electronic System Design, ISED 2012 - Kolkata, West Bengal, India
Duration: 19 Dec 201222 Dec 2012

Other

Other2012 International Symposium on Electronic System Design, ISED 2012
CountryIndia
CityKolkata, West Bengal
Period19/12/1222/12/12

Keywords

  • Discrete Fourier Transform
  • Field Programmable Gate Array(FPGA)
  • Long Term Evolution (LTE)
  • Single Carrier- Frequency Division Multiple Access (SC-FDMA)
  • Systolic Architecture

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