Abstract
A novel design for the implementation of the 2-M x 3-P x 5Q point Discrete Fourier Transform (DFT) computation for Single Carrier-Frequency Division Multiple Access (SC-FDMA) systems as defined by the Long Term Evolution standard is proposed. The design is based on the Systolic Architecture. The decomposition of the DFT computation into factors of two, three, four and five is implemented by a recursive invocation of the Cooley-Tukey Algorithm, with the individual DFTs within each Cooley Tukey iteration implemented using the Winograd Fourier Transform Algorithm (WFTA). The proposed architecture is superior to the Intellectual Property (IP) cores proposed by Xilinx R in that the clock frequency requirements are reduced by a factor of up to 5.2 (approx), resulting in significant savings in the total power dissipation.
| Original language | English |
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| Title of host publication | ISED 2012 |
| Subtitle of host publication | Proceedings of the 2012 International Symposium on Electronic System Design |
| Place of Publication | Piscataway, NJ |
| Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| Pages | 52-55 |
| Number of pages | 4 |
| ISBN (Print) | 9780769549026 |
| DOIs | |
| Publication status | Published - 2012 |
| Externally published | Yes |
| Event | 2012 International Symposium on Electronic System Design, ISED 2012 - Kolkata, West Bengal, India Duration: 19 Dec 2012 → 22 Dec 2012 |
Other
| Other | 2012 International Symposium on Electronic System Design, ISED 2012 |
|---|---|
| Country/Territory | India |
| City | Kolkata, West Bengal |
| Period | 19/12/12 → 22/12/12 |
Keywords
- Discrete Fourier Transform
- Field Programmable Gate Array(FPGA)
- Long Term Evolution (LTE)
- Single Carrier- Frequency Division Multiple Access (SC-FDMA)
- Systolic Architecture