Abstract
Digital harmonic-cancelling sine-wave synthesizers (DHSSs) enable programmable, low cost, spectrally pure, sinusoidal signal synthesis for application areas such as communication systems, and on-chip testing of analog/mixed-signal integrated circuits. The implementation of a DHSS requires a digital-to-analog converter (DAC). However, unlike a conventional binary-coded DAC, the harmonic-cancelling DAC (HC-DAC) used in a DHSS scales the input digital signals by a set of irrational amplitude weights. Consequently, the conventional knowledge of how amplitude resolution affects a binary-coded DAC does not apply to HC-DACs. In this paper, we present a mathematical study of how amplitude resolution and unit-element mismatch affects the signal-todistortion (SDR) ratio of an HC-DAC. The results of the study show that it is possible to find a Pareto optimal value of amplitude resolution for a given HC-DAC with a target SDR. The values of SDR estimated from the mathematical model have been verified against circuit simulation results from two HC-DAC designs created using a 013 μm CMOS technology.
Original language | English |
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Title of host publication | ISCAS 2016 - IEEE International Symposium on Circuits and Systems |
Place of Publication | Piscataway, NJ |
Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
Pages | 2018-2021 |
Number of pages | 4 |
ISBN (Electronic) | 9781479953400 |
DOIs | |
Publication status | Published - 29 Jul 2016 |
Externally published | Yes |
Event | 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada Duration: 22 May 2016 → 25 May 2016 |
Other
Other | 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 |
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Country/Territory | Canada |
City | Montreal |
Period | 22/05/16 → 25/05/16 |
Keywords
- amplitude quantization
- built-in-self-test
- digital sinusoid oscillator
- low harmonic distortion
- signal generator