Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG

Pragya Kushwaha*, K. Bala Krishna, Harshit Agarwal, Sourabh Khandelwal, Juan Pablo Duarte, Chenming Hu, Yogesh Singh Chauhan

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

19 Citations (Scopus)


The channel in Fully Depleted Silicon On Insulator (FDSOI) transistors is completely isolated from the substrate via buried oxide (BOX) and from the sides by shallow trench isolations, which results in high thermal resistance (Rth). Further, Rth increases with reduction in channel length (Lg). In this paper, we have proposed a compact model for the geometry and temperature dependence of Rth in FDSOI transistors. The model is validated against experimental and Technology Computer Aided Design (TCAD) data. The proposed model is implemented in the independent multi-gate model (BSIM-IMG) for FDSOI transistors.

Original languageEnglish
Pages (from-to)171-176
Number of pages6
JournalMicroelectronics Journal
Publication statusPublished - 1 Oct 2016
Externally publishedYes


  • Compact model
  • FDSOI transistor
  • Self-heating effect (SHE)


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