Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG

Pragya Kushwaha; K. Bala Krishna; Harshit Agarwal; Sourabh Khandelwal; Juan Pablo Duarte; Chenming Hu; Yogesh Singh Chauhan

doi:10.1016/j.mejo.2016.07.014

Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG

Pragya Kushwaha^*, K. Bala Krishna, Harshit Agarwal, Sourabh Khandelwal, Juan Pablo Duarte, Chenming Hu, Yogesh Singh Chauhan

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

19 Citations (Scopus)

Abstract

The channel in Fully Depleted Silicon On Insulator (FDSOI) transistors is completely isolated from the substrate via buried oxide (BOX) and from the sides by shallow trench isolations, which results in high thermal resistance (R_th). Further, R_th increases with reduction in channel length (L_g). In this paper, we have proposed a compact model for the geometry and temperature dependence of R_th in FDSOI transistors. The model is validated against experimental and Technology Computer Aided Design (TCAD) data. The proposed model is implemented in the independent multi-gate model (BSIM-IMG) for FDSOI transistors.

Original language	English
Pages (from-to)	171-176
Number of pages	6
Journal	Microelectronics Journal
Volume	56
DOIs	https://doi.org/10.1016/j.mejo.2016.07.014
Publication status	Published - 1 Oct 2016
Externally published	Yes

Keywords

BSIM-IMG
Compact model
FDSOI transistor
Self-heating effect (SHE)

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10.1016/j.mejo.2016.07.014

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@article{bebf8a87301147d48faa1907795c3c2e,

title = "Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG",

abstract = "The channel in Fully Depleted Silicon On Insulator (FDSOI) transistors is completely isolated from the substrate via buried oxide (BOX) and from the sides by shallow trench isolations, which results in high thermal resistance (Rth). Further, Rth increases with reduction in channel length (Lg). In this paper, we have proposed a compact model for the geometry and temperature dependence of Rth in FDSOI transistors. The model is validated against experimental and Technology Computer Aided Design (TCAD) data. The proposed model is implemented in the independent multi-gate model (BSIM-IMG) for FDSOI transistors.",

keywords = "BSIM-IMG, Compact model, FDSOI transistor, Self-heating effect (SHE)",

author = "Pragya Kushwaha and {Bala Krishna}, K. and Harshit Agarwal and Sourabh Khandelwal and Duarte, {Juan Pablo} and Chenming Hu and Chauhan, {Yogesh Singh}",

year = "2016",

month = oct,

day = "1",

doi = "10.1016/j.mejo.2016.07.014",

language = "English",

volume = "56",

pages = "171--176",

journal = "Microelectronics Journal",

issn = "0026-2692",

publisher = "Elsevier",

}

TY - JOUR

T1 - Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG

AU - Kushwaha, Pragya

AU - Bala Krishna, K.

AU - Agarwal, Harshit

AU - Khandelwal, Sourabh

AU - Duarte, Juan Pablo

AU - Hu, Chenming

AU - Chauhan, Yogesh Singh

PY - 2016/10/1

Y1 - 2016/10/1

N2 - The channel in Fully Depleted Silicon On Insulator (FDSOI) transistors is completely isolated from the substrate via buried oxide (BOX) and from the sides by shallow trench isolations, which results in high thermal resistance (Rth). Further, Rth increases with reduction in channel length (Lg). In this paper, we have proposed a compact model for the geometry and temperature dependence of Rth in FDSOI transistors. The model is validated against experimental and Technology Computer Aided Design (TCAD) data. The proposed model is implemented in the independent multi-gate model (BSIM-IMG) for FDSOI transistors.

AB - The channel in Fully Depleted Silicon On Insulator (FDSOI) transistors is completely isolated from the substrate via buried oxide (BOX) and from the sides by shallow trench isolations, which results in high thermal resistance (Rth). Further, Rth increases with reduction in channel length (Lg). In this paper, we have proposed a compact model for the geometry and temperature dependence of Rth in FDSOI transistors. The model is validated against experimental and Technology Computer Aided Design (TCAD) data. The proposed model is implemented in the independent multi-gate model (BSIM-IMG) for FDSOI transistors.

KW - BSIM-IMG

KW - Compact model

KW - FDSOI transistor

KW - Self-heating effect (SHE)

UR - http://www.scopus.com/inward/record.url?scp=84986893203&partnerID=8YFLogxK

U2 - 10.1016/j.mejo.2016.07.014

DO - 10.1016/j.mejo.2016.07.014

M3 - Article

AN - SCOPUS:84986893203

SN - 0026-2692

VL - 56

SP - 171

EP - 176

JO - Microelectronics Journal

JF - Microelectronics Journal

ER -

Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG

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Keywords

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