Three transistor pseudo-static RAM

D. J. Coggins*, D. J. Skellern

*Corresponding author for this work

Research output: Contribution to journalArticle

Abstract

This paper describes the design and successful fabrication of a 2 Kbit RAM macrocell in standard NMOS. A pseudo-static cell yields lower power or more flexible timing than other macrocell RAM options. The interaction between process parameters, circuit design and timing relationships is explored.

Original languageEnglish
Pages (from-to)81-91
Number of pages11
JournalJournal of Electrical and Electronics Engineering, Australia
Volume9
Issue number3
Publication statusPublished - Sep 1989
Externally publishedYes

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