Abstract
This paper describes the design and successful fabrication of a 2 Kbit RAM macrocell in standard NMOS. A pseudo-static cell yields lower power or more flexible timing than other macrocell RAM options. The interaction between process parameters, circuit design and timing relationships is explored.
| Original language | English |
|---|---|
| Pages (from-to) | 81-91 |
| Number of pages | 11 |
| Journal | Journal of Electrical and Electronics Engineering, Australia |
| Volume | 9 |
| Issue number | 3 |
| Publication status | Published - Sept 1989 |
| Externally published | Yes |