Three transistor pseudo-static RAM

D. J. Coggins; D. J. Skellern

Three transistor pseudo-static RAM

D. J. Coggins^*, D. J. Skellern

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

Abstract

This paper describes the design and successful fabrication of a 2 Kbit RAM macrocell in standard NMOS. A pseudo-static cell yields lower power or more flexible timing than other macrocell RAM options. The interaction between process parameters, circuit design and timing relationships is explored.

Original language	English
Pages (from-to)	81-91
Number of pages	11
Journal	Journal of Electrical and Electronics Engineering, Australia
Volume	9
Issue number	3
Publication status	Published - Sept 1989
Externally published	Yes

Cite this

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title = "Three transistor pseudo-static RAM",

abstract = "This paper describes the design and successful fabrication of a 2 Kbit RAM macrocell in standard NMOS. A pseudo-static cell yields lower power or more flexible timing than other macrocell RAM options. The interaction between process parameters, circuit design and timing relationships is explored.",

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Three transistor pseudo-static RAM

Abstract

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