TLegUp

a TMR code generation tool for SRAM-based FPGA applications using HLS

Ganghee Lee, Dimitris Agiakatsikas, Tong Wu, Ediz Cetin, Oliver Diessel

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contribution

8 Citations (Scopus)
1 Downloads (Pure)

Abstract

We present TLegUp, an extension of LegUp, that automatically generates Triple Modular Redundant designs for FPGAs from C programs. TLegUp is expected to improve the productivity of application designers for space, to allow designers to experiment with alternative application partitioning, voter insertion and fault-tolerant aware scheduling and binding algorithms, and to support the automatic insertion of the infrastructure needed to run a fault-tolerant system. In this paper, we examine TLegUp's capacity to make use of both combinational and sequential voters by triplicating a design before scheduling and binding occur. In contrast, traditional RTL-based tools are constrained to use only combinational voters so as to preserve the scheduling and binding of the design, critical path lengths are consequently increased. We compare the use of sequential and combinational voters for a range of benchmarks implemented on a Xilinx Virtex-6 FPGA in terms of: (i) maximum operating frequency, (ii) latency, (iii) execution time, and (iv) soft-error sensitivity. Compared to the use of combinational voters, the use of sequential voters reduces the application execution time on the CHStone benchmark suite by 4% on average.

Original languageEnglish
Title of host publication2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines
Subtitle of host publicationproceedings
Place of PublicationPiscataway, NJ, USA
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages129-132
Number of pages4
ISBN (Electronic)9781538640371
ISBN (Print)9781538640388
DOIs
Publication statusPublished - 2017
Event25th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017 - Napa, United States
Duration: 30 Apr 20172 May 2017
Conference number: 25

Conference

Conference25th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017
CountryUnited States
CityNapa
Period30/04/172/05/17

Keywords

  • Benchmark testing
  • Clocks
  • Field programmable gate arrays
  • Hardware design languages
  • Registers
  • Tools
  • Tunneling magnetoresistance
  • FPGA
  • HLS
  • TMR

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  • Cite this

    Lee, G., Agiakatsikas, D., Wu, T., Cetin, E., & Diessel, O. (2017). TLegUp: a TMR code generation tool for SRAM-based FPGA applications using HLS. In 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines: proceedings (pp. 129-132). Piscataway, NJ, USA: Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/FCCM.2017.57