TOPOLOGIZER: an expert system translator of transistor connectivity to symbolic cell layout

Paul W. Kollaritsch; Neil H E Weste

doi:10.1109/JSSC.1985.1052385

TOPOLOGIZER: an expert system translator of transistor connectivity to symbolic cell layout

Paul W. Kollaritsch, Neil H E Weste

Research output: Contribution to journal › Article › peer-review

26 Citations (Scopus)

Abstract

TOPOLOGIZER is an expert system for the design of CMOS cells. TOPOLOGIZER uses heuristics (rules) specified by an expert designer to produce a custom-fit symbolic leaf-cell from a transistor connection description and a description of the environment in which the cell will reside. A symbolic layout system converts the symbolic description to a mask level description.

Original language	English
Pages (from-to)	799-804
Number of pages	6
Journal	IEEE Journal of Solid-State Circuits
Volume	20
Issue number	3
DOIs	https://doi.org/10.1109/JSSC.1985.1052385
Publication status	Published - 1985
Externally published	Yes

Access to Document

10.1109/JSSC.1985.1052385

Cite this

@article{e2a794424ff54d269efa184f4399bf08,

title = "TOPOLOGIZER: an expert system translator of transistor connectivity to symbolic cell layout",

abstract = "TOPOLOGIZER is an expert system for the design of CMOS cells. TOPOLOGIZER uses heuristics (rules) specified by an expert designer to produce a custom-fit symbolic leaf-cell from a transistor connection description and a description of the environment in which the cell will reside. A symbolic layout system converts the symbolic description to a mask level description.",

author = "Kollaritsch, \{Paul W.\} and Weste, \{Neil H E\}",

year = "1985",

doi = "10.1109/JSSC.1985.1052385",

language = "English",

volume = "20",

pages = "799--804",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

number = "3",

}

TY - JOUR

T1 - TOPOLOGIZER

T2 - an expert system translator of transistor connectivity to symbolic cell layout

AU - Kollaritsch, Paul W.

AU - Weste, Neil H E

PY - 1985

Y1 - 1985

N2 - TOPOLOGIZER is an expert system for the design of CMOS cells. TOPOLOGIZER uses heuristics (rules) specified by an expert designer to produce a custom-fit symbolic leaf-cell from a transistor connection description and a description of the environment in which the cell will reside. A symbolic layout system converts the symbolic description to a mask level description.

AB - TOPOLOGIZER is an expert system for the design of CMOS cells. TOPOLOGIZER uses heuristics (rules) specified by an expert designer to produce a custom-fit symbolic leaf-cell from a transistor connection description and a description of the environment in which the cell will reside. A symbolic layout system converts the symbolic description to a mask level description.

UR - https://www.scopus.com/pages/publications/0021445721

U2 - 10.1109/JSSC.1985.1052385

DO - 10.1109/JSSC.1985.1052385

M3 - Article

AN - SCOPUS:0021445721

SN - 0018-9200

VL - 20

SP - 799

EP - 804

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 3

ER -

TOPOLOGIZER: an expert system translator of transistor connectivity to symbolic cell layout

Abstract

Access to Document

Other files and links

Fingerprint

Cite this