Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration

Ediz Cetin, Oliver Diessel, Lingkan Gong, Victor Lai

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contribution

15 Citations (Scopus)

Abstract

Field-Programmable Gate Array (FPGA) systems are increasingly susceptible to radiation-induced Single Event Upsets (SEUs). Application circuits are most commonly protected from SEUs using Triple Modular Redundancy (TMR) and scrubbing to eliminate configuration memory errors. This paper focuses on implementing circuits that recover from SEUs within a specified maximum recovery period, a practical requirement not previously addressed. We develop a recovery time model, describe a scalable reconfiguration control network, and investigate the performance of a representative TMR system implemented using our approach. The results demonstrate that modular reconfiguration eliminate configuration errors more responsively and using less energy than scrubbing. However, these benefits are achieved at the cost of additional area, minor speed penalties, and greater design complexity.

Original languageEnglish
Title of host publication2013 23rd International Conference on Field Programmable Logic and Applications (FPL 2013)
Subtitle of host publicationproceedings
EditorsJoão M. P. Cardoso, Katherine (Compton) Morrow, Pedro C. Diniz
Place of PublicationPiscataway, NJ
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages4
ISBN (Electronic)9781479900046
DOIs
Publication statusPublished - 2013
Externally publishedYes
EventInternational Conference on Field Programmable Logic and Applications (23rd : 2013) - Porto, Portugal
Duration: 2 Sep 20134 Sep 2013
Conference number: 23rd

Other

OtherInternational Conference on Field Programmable Logic and Applications (23rd : 2013)
Abbreviated titleFPL 2013
CountryPortugal
CityPorto
Period2/09/134/09/13

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  • Cite this

    Cetin, E., Diessel, O., Gong, L., & Lai, V. (2013). Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration. In J. M. P. Cardoso, K. (Compton) Morrow, & P. C. Diniz (Eds.), 2013 23rd International Conference on Field Programmable Logic and Applications (FPL 2013): proceedings Piscataway, NJ: Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/FPL.2013.6645571