Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration

Ediz Cetin; Oliver Diessel; Lingkan Gong; Victor Lai

doi:10.1109/FPL.2013.6645571

Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration

Ediz Cetin, Oliver Diessel, Lingkan Gong, Victor Lai

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

15 Citations (Scopus)

Abstract

Field-Programmable Gate Array (FPGA) systems are increasingly susceptible to radiation-induced Single Event Upsets (SEUs). Application circuits are most commonly protected from SEUs using Triple Modular Redundancy (TMR) and scrubbing to eliminate configuration memory errors. This paper focuses on implementing circuits that recover from SEUs within a specified maximum recovery period, a practical requirement not previously addressed. We develop a recovery time model, describe a scalable reconfiguration control network, and investigate the performance of a representative TMR system implemented using our approach. The results demonstrate that modular reconfiguration eliminate configuration errors more responsively and using less energy than scrubbing. However, these benefits are achieved at the cost of additional area, minor speed penalties, and greater design complexity.

Original language	English
Title of host publication	2013 23rd International Conference on Field Programmable Logic and Applications (FPL 2013)
Subtitle of host publication	proceedings
Editors	João M. P. Cardoso, Katherine (Compton) Morrow, Pedro C. Diniz
Place of Publication	Piscataway, NJ
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Number of pages	4
ISBN (Electronic)	9781479900046
DOIs	https://doi.org/10.1109/FPL.2013.6645571
Publication status	Published - 2013
Externally published	Yes
Event	International Conference on Field Programmable Logic and Applications (23rd : 2013) - Porto, Portugal Duration: 2 Sep 2013 → 4 Sep 2013 Conference number: 23rd

Other

Other	International Conference on Field Programmable Logic and Applications (23rd : 2013)
Abbreviated title	FPL 2013
Country/Territory	Portugal
City	Porto
Period	2/09/13 → 4/09/13

Access to Document

10.1109/FPL.2013.6645571

Cite this

Cetin, E., Diessel, O., Gong, L., & Lai, V. (2013). Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration. In J. M. P. Cardoso, K. (Compton) Morrow, & P. C. Diniz (Eds.), 2013 23rd International Conference on Field Programmable Logic and Applications (FPL 2013): proceedings Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/FPL.2013.6645571

Cetin, Ediz ; Diessel, Oliver ; Gong, Lingkan ; Lai, Victor. / Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration. 2013 23rd International Conference on Field Programmable Logic and Applications (FPL 2013): proceedings. editor / João M. P. Cardoso ; Katherine (Compton) Morrow ; Pedro C. Diniz. Piscataway, NJ : Institute of Electrical and Electronics Engineers (IEEE), 2013.

@inproceedings{4e040480db2341869c1dbfab3035454c,

title = "Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration",

abstract = "Field-Programmable Gate Array (FPGA) systems are increasingly susceptible to radiation-induced Single Event Upsets (SEUs). Application circuits are most commonly protected from SEUs using Triple Modular Redundancy (TMR) and scrubbing to eliminate configuration memory errors. This paper focuses on implementing circuits that recover from SEUs within a specified maximum recovery period, a practical requirement not previously addressed. We develop a recovery time model, describe a scalable reconfiguration control network, and investigate the performance of a representative TMR system implemented using our approach. The results demonstrate that modular reconfiguration eliminate configuration errors more responsively and using less energy than scrubbing. However, these benefits are achieved at the cost of additional area, minor speed penalties, and greater design complexity.",

author = "Ediz Cetin and Oliver Diessel and Lingkan Gong and Victor Lai",

year = "2013",

doi = "10.1109/FPL.2013.6645571",

language = "English",

editor = "Cardoso, {Jo{\~a}o M. P.} and {(Compton) Morrow}, Katherine and Diniz, {Pedro C.}",

booktitle = "2013 23rd International Conference on Field Programmable Logic and Applications (FPL 2013)",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "International Conference on Field Programmable Logic and Applications (23rd : 2013), FPL 2013 ; Conference date: 02-09-2013 Through 04-09-2013",

}

Cetin, E, Diessel, O, Gong, L & Lai, V 2013, Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration. in JMP Cardoso, K (Compton) Morrow & PC Diniz (eds), 2013 23rd International Conference on Field Programmable Logic and Applications (FPL 2013): proceedings. Institute of Electrical and Electronics Engineers (IEEE), Piscataway, NJ, International Conference on Field Programmable Logic and Applications (23rd : 2013), Porto, Portugal, 2/09/13. https://doi.org/10.1109/FPL.2013.6645571

Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration. / Cetin, Ediz; Diessel, Oliver; Gong, Lingkan; Lai, Victor.

2013 23rd International Conference on Field Programmable Logic and Applications (FPL 2013): proceedings. ed. / João M. P. Cardoso; Katherine (Compton) Morrow; Pedro C. Diniz. Piscataway, NJ : Institute of Electrical and Electronics Engineers (IEEE), 2013.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

TY - GEN

T1 - Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration

AU - Cetin, Ediz

AU - Diessel, Oliver

AU - Gong, Lingkan

AU - Lai, Victor

N1 - Conference code: 23rd

PY - 2013

Y1 - 2013

N2 - Field-Programmable Gate Array (FPGA) systems are increasingly susceptible to radiation-induced Single Event Upsets (SEUs). Application circuits are most commonly protected from SEUs using Triple Modular Redundancy (TMR) and scrubbing to eliminate configuration memory errors. This paper focuses on implementing circuits that recover from SEUs within a specified maximum recovery period, a practical requirement not previously addressed. We develop a recovery time model, describe a scalable reconfiguration control network, and investigate the performance of a representative TMR system implemented using our approach. The results demonstrate that modular reconfiguration eliminate configuration errors more responsively and using less energy than scrubbing. However, these benefits are achieved at the cost of additional area, minor speed penalties, and greater design complexity.

AB - Field-Programmable Gate Array (FPGA) systems are increasingly susceptible to radiation-induced Single Event Upsets (SEUs). Application circuits are most commonly protected from SEUs using Triple Modular Redundancy (TMR) and scrubbing to eliminate configuration memory errors. This paper focuses on implementing circuits that recover from SEUs within a specified maximum recovery period, a practical requirement not previously addressed. We develop a recovery time model, describe a scalable reconfiguration control network, and investigate the performance of a representative TMR system implemented using our approach. The results demonstrate that modular reconfiguration eliminate configuration errors more responsively and using less energy than scrubbing. However, these benefits are achieved at the cost of additional area, minor speed penalties, and greater design complexity.

UR - http://www.scopus.com/inward/record.url?scp=84898636355&partnerID=8YFLogxK

U2 - 10.1109/FPL.2013.6645571

DO - 10.1109/FPL.2013.6645571

M3 - Conference proceeding contribution

AN - SCOPUS:84898636355

BT - 2013 23rd International Conference on Field Programmable Logic and Applications (FPL 2013)

A2 - Cardoso, João M. P.

A2 - (Compton) Morrow, Katherine

A2 - Diniz, Pedro C.

PB - Institute of Electrical and Electronics Engineers (IEEE)

CY - Piscataway, NJ

T2 - International Conference on Field Programmable Logic and Applications (23rd : 2013)

Y2 - 2 September 2013 through 4 September 2013

ER -

Cetin E, Diessel O, Gong L, Lai V. Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration. In Cardoso JMP, (Compton) Morrow K, Diniz PC, editors, 2013 23rd International Conference on Field Programmable Logic and Applications (FPL 2013): proceedings. Piscataway, NJ: Institute of Electrical and Electronics Engineers (IEEE). 2013 https://doi.org/10.1109/FPL.2013.6645571

Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration

Abstract

Other

Access to Document

Other files and links

Fingerprint

Cite this