Transient SPICE model for trap related current lag in devices

Traps at the surface of devices cause gate lag, which is the delayed response of drain current to a step change of gate voltage. The effect of gate lag limits the performance of devices and integrated circuits such as digital circuits, digital radio systems. The manifestation of gate lag in the frequency domain is transconductance and drain conductance dispersion. Gate lag is usually caused by surface hole trapping. Traps at the surface are charged negatively during turn-off of the devices. The negative charge turns the device further off. After turnon, these negative charges decay by means of capturing holes, which turns the device further on. The finite time related to trap charging and discharging results in gate lag. Pulsed measurements have been carried out to observe and measure this current lag in HEMT devices. Drain voltage has been found to have significant effect on the time constant of carrier trapping. Prior knowledge of the lag enables one to modify the design and selecting proper bias point for a specific application. For this purpose, a SPICE model has been developed to simulate gate lag in devices. The time lag is modelled by an RC time constant. Depending on the drain voltage, this time constant changes from 10ms to lus. The model also predicts the transient gate current for gate voltage going down towards pinch-off. The model has further been tested for near half the saturated drain current. Two-tone intermodulation simulation is being investigated with the model.