Virtual grid symbolic layout

David Tana*, Neil Weste

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contributionpeer-review

4 Citations (Scopus)

Abstract

The authors describe the compaction methodology and certain features of the compactors used at Symbolics. These tools have been used as the sole physical layout tool for a 300,000-transistor single-chip Lisp microprocessor. The three compactors and compactor tools amount to 6000 lines of Common Lisp on a Symbolics Lisp Machine. The code makes heavy use of the object-oriented Flavor system. Times have been measured for a Symbolics 3640 with 24 Mb of RAM running Genera 7. 1.

Original languageEnglish
Title of host publicationUnknown Host Publication Title
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages192-196
Number of pages5
ISBN (Print)0818608021
Publication statusPublished - 1987
Externally publishedYes

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