VLSI architecture of full-search variable-block-size motion estimation for HEVC video encoding

Niras Cheeckottu Vayalil*, Yinan Kong

*Corresponding author for this work

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

Motion estimation (ME) is the most computationally intensive task in video encoding. This study proposes a full-search variable-block-size ME for the high-efficiency video coding or H.265 specification. The proposed method reduces memory requirements to a large extent by following a Morton order for data reading and a sum of absolute differences reuse strategy. The data bandwidth demand is also diminished by broadcasting data into multiple processing elements. This ME accelerator supports variable-block-size prediction blocks ranging from 8 × 4 to 64 × 64, and is reconfigurable in various search ranges for a trade-off between performance and area. The proposed method for very-large-scale integration (VLSI) architecture is synthesized with 32 nm technology, and is capable of real-time encoding of ultra-high-definition (4K-UHD, at 30 Hz) video with a search range of 64 pixels in both horizontal and vertical directions, operating at a frequency of 282 MHz.
Original languageEnglish
Pages (from-to)543-548
Number of pages6
JournalIET Circuits, Devices and Systems
Volume11
Issue number6
DOIs
Publication statusPublished - 1 Nov 2017

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