Write buffer-aware address mapping for NAND flash memory devices

Sungmin Park; Hoyoung Jung; Hyoki Shim; Sooyong Kang; Jaehyuk Cha

doi:10.1109/MASCOT.2008.4770592

Write buffer-aware address mapping for NAND flash memory devices

Sungmin Park^*, Hoyoung Jung, Hyoki Shim, Sooyong Kang, Jaehyuk Cha

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

2 Citations (Scopus)

Abstract

By using small-sized, next-generation NVRAM (such as MRAM, FeRAM and PRAM) as a write buffer, we can improve the overall performance of the NAND flash memorybased storage systems. However, traditional address mapping algorithms in Flash Translation Layer (FTL) software were designed without any consideration of the existence of write buffer. In this paper, we propose a novel write buffer-aware flash translation layer algorithm, optimistic FTL, which is designed to harmonize well with NVRAM write buffers. Simulation results show that the proposed optimistic FTL outperforms previous log block-based FTL algorithms.

Original language	English
Title of host publication	2008 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS
Place of Publication	Piscataway, New Jersey
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	1-2
Number of pages	2
ISBN (Print)	9781424428182
DOIs	https://doi.org/10.1109/MASCOT.2008.4770592
Publication status	Published - 2008
Externally published	Yes
Event	2008 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS - Baltimore, MD, United States Duration: 8 Sept 2008 → 20 Sept 2008

Other

Other	2008 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS
Country/Territory	United States
City	Baltimore, MD
Period	8/09/08 → 20/09/08

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10.1109/MASCOT.2008.4770592

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Park, S., Jung, H., Shim, H., Kang, S., & Cha, J. (2008). Write buffer-aware address mapping for NAND flash memory devices. In 2008 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS (pp. 1-2). Article 4770592 Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/MASCOT.2008.4770592

@inproceedings{7f4153bf969d4128bfc79eb59299a894,

title = "Write buffer-aware address mapping for NAND flash memory devices",

abstract = "By using small-sized, next-generation NVRAM (such as MRAM, FeRAM and PRAM) as a write buffer, we can improve the overall performance of the NAND flash memorybased storage systems. However, traditional address mapping algorithms in Flash Translation Layer (FTL) software were designed without any consideration of the existence of write buffer. In this paper, we propose a novel write buffer-aware flash translation layer algorithm, optimistic FTL, which is designed to harmonize well with NVRAM write buffers. Simulation results show that the proposed optimistic FTL outperforms previous log block-based FTL algorithms.",

author = "Sungmin Park and Hoyoung Jung and Hyoki Shim and Sooyong Kang and Jaehyuk Cha",

year = "2008",

doi = "10.1109/MASCOT.2008.4770592",

language = "English",

isbn = "9781424428182",

pages = "1--2",

booktitle = "2008 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "2008 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS ; Conference date: 08-09-2008 Through 20-09-2008",

}

Park, S, Jung, H, Shim, H, Kang, S & Cha, J 2008, Write buffer-aware address mapping for NAND flash memory devices. in 2008 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS., 4770592, Institute of Electrical and Electronics Engineers (IEEE), Piscataway, New Jersey, pp. 1-2, 2008 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS, Baltimore, MD, United States, 8/09/08. https://doi.org/10.1109/MASCOT.2008.4770592

Write buffer-aware address mapping for NAND flash memory devices. / Park, Sungmin; Jung, Hoyoung; Shim, Hyoki et al.
2008 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS. Piscataway, New Jersey: Institute of Electrical and Electronics Engineers (IEEE), 2008. p. 1-2 4770592.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

TY - GEN

T1 - Write buffer-aware address mapping for NAND flash memory devices

AU - Park, Sungmin

AU - Jung, Hoyoung

AU - Shim, Hyoki

AU - Kang, Sooyong

AU - Cha, Jaehyuk

PY - 2008

Y1 - 2008

N2 - By using small-sized, next-generation NVRAM (such as MRAM, FeRAM and PRAM) as a write buffer, we can improve the overall performance of the NAND flash memorybased storage systems. However, traditional address mapping algorithms in Flash Translation Layer (FTL) software were designed without any consideration of the existence of write buffer. In this paper, we propose a novel write buffer-aware flash translation layer algorithm, optimistic FTL, which is designed to harmonize well with NVRAM write buffers. Simulation results show that the proposed optimistic FTL outperforms previous log block-based FTL algorithms.

AB - By using small-sized, next-generation NVRAM (such as MRAM, FeRAM and PRAM) as a write buffer, we can improve the overall performance of the NAND flash memorybased storage systems. However, traditional address mapping algorithms in Flash Translation Layer (FTL) software were designed without any consideration of the existence of write buffer. In this paper, we propose a novel write buffer-aware flash translation layer algorithm, optimistic FTL, which is designed to harmonize well with NVRAM write buffers. Simulation results show that the proposed optimistic FTL outperforms previous log block-based FTL algorithms.

UR - http://www.scopus.com/inward/record.url?scp=65949122100&partnerID=8YFLogxK

U2 - 10.1109/MASCOT.2008.4770592

DO - 10.1109/MASCOT.2008.4770592

M3 - Conference proceeding contribution

AN - SCOPUS:65949122100

SN - 9781424428182

SP - 1

EP - 2

BT - 2008 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS

PB - Institute of Electrical and Electronics Engineers (IEEE)

CY - Piscataway, New Jersey

T2 - 2008 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS

Y2 - 8 September 2008 through 20 September 2008

ER -

Write buffer-aware address mapping for NAND flash memory devices

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