Write buffer-aware address mapping for NAND flash memory devices

Sungmin Park*, Hoyoung Jung, Hyoki Shim, Sooyong Kang, Jaehyuk Cha

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contribution

2 Citations (Scopus)

Abstract

By using small-sized, next-generation NVRAM (such as MRAM, FeRAM and PRAM) as a write buffer, we can improve the overall performance of the NAND flash memorybased storage systems. However, traditional address mapping algorithms in Flash Translation Layer (FTL) software were designed without any consideration of the existence of write buffer. In this paper, we propose a novel write buffer-aware flash translation layer algorithm, optimistic FTL, which is designed to harmonize well with NVRAM write buffers. Simulation results show that the proposed optimistic FTL outperforms previous log block-based FTL algorithms.

Original languageEnglish
Title of host publication2008 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS
Place of PublicationPiscataway, New Jersey
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages1-2
Number of pages2
ISBN (Print)9781424428182
DOIs
Publication statusPublished - 2008
Externally publishedYes
Event2008 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS - Baltimore, MD, United States
Duration: 8 Sep 200820 Sep 2008

Other

Other2008 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS
CountryUnited States
CityBaltimore, MD
Period8/09/0820/09/08

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